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devices incorporated video imaging products 1 lf43168 dual 8-tap fir filter 03/28/2000Clds.43168-h q q q q q 66 mhz data and computation rate q q q q q two independent 8-tap or single 16-tap fir filters q q q q q 10-bit data and coefficient inputs q q q q q 32 programmable coefficient sets q q q q q supports interleaved coefficient sets q q q q q user programmable decimation up to 16:1 q q q q q maximum of 256 fir filter taps, 16 x 16 2-d kernels, or 10 x 20-bit data and coefficients q q q q q replaces harris hsp43168 q q q q q package styles available: ? 84-pin plastic lcc, j-lead ? 100-pin plastic quad flatpack features description lf43168 dual 8-tap fir filter devices incorporated the lf43168 is a high-speed dual fir filter capable of filtering data at real- time video rates. the device contains two fir filters which may be used as two separate filters or cascaded to form one filter. the input and coeffi- cient data are both 10-bits and can be in unsigned, twos complement, or mixed mode format. the filter architecture is optimized for symmetric coefficient sets. when symmetric coefficient sets are used, each filter can be configured as an 8-tap fir filter. if the two filters are cas- caded, a 16-tap fir filter can be implemented. when asymmetric coefficient sets are used, each filter is configured as a 4-tap fir filter. if both filters are cascaded, an 8-tap filter can be implemented. the lf43168 can decimate the output data by as much as 16:1. when the device is pro- grammed to decimate, the number of clock cycles available to calculate filter taps increases. when configured for 16:1 decimation, each filter can be configured as a 128-tap fir filter (if symmetric coefficient sets are used). by cascading these two filters, the device can be configured as a 256-tap fir filter. there is on-chip storage for 32 different sets of coefficients. each set consists of eight coefficients. access to more than one coefficient set facilitates adaptive filtering opera- tions. the 28-bit filter output can be rounded from 8 to 19 bits. lf43168 b lock d iagram cin 9-0 a 8-0 wr control 10 9 csel 4-0 5 coefficient bank a coefficient bank b filter cell a filter cell b mux ina 9-0 inb 9-0 / out 8-0 mux/adder 9 19 mux oel oeh out 27-9 10 10 9
devices incorporated lf43168 dual 8-tap fir filter 2 video imaging products 03/28/2000Clds.43168-h f igure 1. lf43168 f unctional b lock d iagram txfr 4 3 mux 3 3 3 shften ina 9-0 mux inb 9-0 / out 8-0 10 mux_ctrl to all decimation registers cin 9-0 a 8-0 wr control coef bank 0 coef bank 1 coef bank 2 coef bank 3 3 fwrd rvrs to all alus to all alus odd/even (to all alus) mux_ctrl round_ctrl 3 alu 1-16 1-16 1-16 1-16 1-16 1-16 mux 0 mux mux demux 10 9 1-16 mux mux_ctrl 1-16 1-16 1-16 1-16 1-16 1-16 mux lifo a coef bank 0 coef bank 1 coef bank 2 coef bank 3 mux 0 lifo b 1-16 mux demux lifo a lifo b 1-16 mux_ctrl 5 accen mux/ adder round_ctrl 6 mux 1-0 4 csel 4-0 5 2 2 9 19 out 27-9 oel oeh clk n data clk n+1 data clk n data clk n+1 data 10 ab alu ab alu ab alu ab alu ab alu ab alu ab alu ab fir filter a fir filter b decimation registers decimation registers note: numbers in registers indicate number of pipeline delays. clk 9
devices incorporated video imaging products 3 lf43168 dual 8-tap fir filter 03/28/2000Clds.43168-h signal definitions power v cc and gnd +5 v power supply. all pins must be connected. clock clk master clock the rising edge of clk strobes all enabled registers. inputs ina 9-0 data input (fir filter a) ina 9-0 is the 10-bit registered data input port for fir filter a. ina 9-0 can also be used to send data to fir filter b. data is latched on the rising edge of clk. inb 9-0 data input (fir filter b) inb 9-0 is the 10-bit registered data input port for fir filter b. data is latched on the rising edge of clk. inb 9-1 is also used as out 8-0 , the nine least significant bits of the data output port (see out 27-0 section). cin 9-0 coefficient/control data input cin 9-0 is the data input port for the coefficient and control registers. data is latched on the rising edge of wr. a 8-0 coefficient/control address a 8-0 provides the write address for data on cin 9-0 . data is latched on the falling edge of wr. wr coefficient/control write the rising edge of wr latches data on cin 9-0 into the coefficient/control register addressed by a 8-0 . csel 4-0 coefficient select csel 4-0 determines which set of coefficients is sent to the multipliers in both fir filters. data is latched on the rising edge of clk. outputs out 27-0 data output out 27-0 is the 28-bit registered data output port. out 8-0 is also used as inb 9-1 , the nine most significant bits of the fir filter b data input port (see inb 9-0 section). if both filters are configured for even-symmetric coefficients, and both input and coefficient data is unsigned, the filter output data will be unsigned. other- wise, the output data will be in twos complement format. controls shften shift enable when shften is low, data on ina 9-0 and inb 9-0 can be latched into the device and data can be shifted through the decimation registers. when shften is high, data on ina 9-0 and inb 9-0 can not be latched into the device and data in the input and decimation registers is held. this signal is latched on the rising edge of clk. fwrd forward alu input when fwrd is low, data from the forward decimation path is sent to the a inputs on the alus. when fwrd is high, 0 is sent to the a inputs on the alus. this signal is latched on the rising edge of clk. rvrs reverse alu input when rvrs is low, data from the reverse decimation path is sent to the b inputs on the alus. when rvrs is high, 0 is sent to the b inputs on the alus. this signal is latched on the rising edge of clk. txfr lifo transfer control when txfr goes low, the lifo sending data to the reverse decimation path becomes the lifo receiving data from the forward decimation path, and the lifo receiving data from the forward decimation path becomes the lifo sending data to the reverse decimation path. the device must see a high to low transition of txfr in order to switch lifos. this signal is latched on the rising edge of clk. f igure 2 a .i nput f ormats 987 210 2 0 2 C1 2 C2 2 C7 2 C8 2 C9 987 210 2 0 2 C1 2 C2 2 C7 2 C8 2 C9 987 210 C2 0 (sign) 2 C1 2 C2 2 C7 2 C8 2 C9 987 210 C2 0 (sign) 2 C1 2 C2 2 C7 2 C8 2 C9 fractional unsigned fractional two's complement data coefficient f igure 2 b .o utput f ormats 27 26 25 2 1 0 2 9 2 8 2 7 2 C16 2 C17 2 C18 27 26 25 2 1 0 C2 9 (sign) 2 8 2 7 2 C16 2 C17 2 C18 fractional unsigned fractional two's complement
devices incorporated lf43168 dual 8-tap fir filter 4 video imaging products 03/28/2000Clds.43168-h accen accumulate enable when accen is high, both accumu- lators are enabled for accumulation and writing to the accumulator output registers is disabled (the registers hold their values). when accen goes low, accumulation is halted (by sending zeros to the accumulator feedback inputs) and writing to the accumulator output registers is enabled. this signal is latched on the rising edge of clk. mux 1-0 mux/adder control mux 1-0 controls the mux/adder as shown in table 3. data is latched on the rising edge of clk. oel output enable low when oel is low, out 8-0 is enabled for output and inb 9-1 can not be used. when oel is high, out 8-0 is placed in a high-impedance state and inb 9-1 is available for data input. oeh output enable high when oeh is low, out 27-9 is enabled for output. when oeh is high, out 27-9 is placed in a high- impedance state. functional description control registers there are two control registers which determine how the lf43168 is config- ured. tables 1 and 2 show how each register is organized. data on cin 9-0 is latched into the addressed control register on the rising edge of wr. address data is input on a 8-0 . con- trol register 0 is written to using address 000h. control register 1 is written to using address 001h (note that addresses 002h to 0ffh are reserved and should not be written to). when a control register is written to, a reset occurs which lasts for 6 clk cycles from when wr goes high. this reset does not alter any data in the coefficient banks. control data can be loaded asynchronously to clk. bits 0-3 of control register 0 control the decimation registers. the decima- tion factor and decimation register delay length is set using these bits. bit 4 determines if fir filters a and b operate separately as two filters or together as one filter. bit 5 is used to select even or odd-symmetric coeffi- cients. bits 6 and 7 determine if there are an even or odd number of taps in filters a and b respectively. when the fir filters are set to operate as two separate filters, bit 8 selects either ina 9-0 or inb 9-0 as the filter b input source. bit 9 determines if the coeffi- cient set used is interleaved or non- interleaved (see interleaved coeffi- cient filters section). most applica- tions use non-interleaved coefficient sets (bit 9 set to 0). bits 0 and 1 of control register 1 determine the input and coefficient data formats respectively for filter a. bits 2 and 3 determine the input and coefficient data formats respectively for filter b. bit 4 is used to enable or disable data reversal on the reverse decimation path. when data reversal is enabled, the data order is reversed before being sent to the reverse decimation path. bits 5-8 select where rounding will occur on the output data (see mux/adder section). bit 9 enables or disables output rounding. coefficient banks the coefficient banks supply coeffi- cient data to the multipliers in both fir filters. the lf43168 can store 32 different coefficient sets. a coefficient bits function description 0C3 decimation factor/ 0000 = no decimation, delay by 1 decimation register delay length 0001 = decimate by 2, delay by 2 0010 = decimate by 3, delay by 3 0011 = decimate by 4, delay by 4 0100 = decimate by 5, delay by 5 0101 = decimate by 6, delay by 6 0110 = decimate by 7, delay by 7 0111 = decimate by 8, delay by 8 1000 = decimate by 9, delay by 9 1001 = decimate by 10, delay by 10 1010 = decimate by 11, delay by 11 1011 = decimate by 12, delay by 12 1100 = decimate by 13, delay by 13 1101 = decimate by 14, delay by 14 1110 = decimate by 15, delay by 15 1111 = decimate by 16, delay by 16 4 filter mode select 0 = single filter mode 1 = dual filter mode 5 coefficient symmetry select 0 = even-symmetric coefficients 1 = odd-symmetric coefficients 6 fir filter a: odd/even taps 0 = odd number of filter taps 1 = even number of filter taps 7 fir filter b: odd/even taps 0 = odd number of filter taps 1 = even number of filter taps 8 fir filter b input source 0 = input from ina 9-0 1 = input from inb 9-0 9 interleaved/non-interleaved 0 = non-interleaved coefficient sets coefficient sets 1 = interleaved coefficient sets t able 1. c ontrol r egister 0 C a ddress 000h
devices incorporated video imaging products 5 lf43168 dual 8-tap fir filter 03/28/2000Clds.43168-h set consists of 8 coefficient values. each bank can hold 32 10-bit values. csel 4-0 is used to select which coefficient set is sent to the filter multipliers. the coefficient set fed to the multipliers may be switched every clk cycle if desired. data on cin 9-0 is latched into the addressed coefficient bank on the rising edge of wr. address data is input on a 8-0 and is decoded as follows: a 1-0 determines the bank number (00, 01, 10, and 11 correspond to banks 0, 1, 2, and 3 respectively), a 2 determines which filter (0 = filter a, 1 = filter b), a 7-3 determines which set number the coefficient is in, and a 8 must be set to 1. for example, an address of 100111011 will load coefficient set 7 in bank 3 of filter a with data. coeffi- cient data can be loaded asynchro- nously to clk. decimation registers the decimation registers are provided to take advantage of symmetric filter coefficients and to provide data storage for 2-d filtering. the outputs of the registers are fed into the alus. both inputs to an alu need to be multiplied by the same filter coeffi- cient. by adding or subtracting the two data inputs together before being sent to the filter multiplier, the num- ber of filter taps needed is cut in half. therefore, an 8-tap fir filter can be made with only four multipliers. the decimation registers are divided into two groups, the forward and reverse decimation registers. as can be seen in figure 1, data flows left to right through the forward decimation registers and right to left through the reverse decimation registers. the decimation registers can be pro- bits function description 0 fir filter a input data format 0 = unsigned 1 = twos complement 1 fir filter a coefficient format 0 = unsigned 1 = twos complement 2 fir filter b input data format 0 = unsigned 1 = twos complement 3 fir filter b coefficient format 0 = unsigned 1 = twos complement 4 data order reversal enable 0 = enabled 1 = disabled 5C8 output round position 0000 = 2 C10 0001 = 2 C9 0010 = 2 C8 0011 = 2 C7 0100 = 2 C6 0101 = 2 C5 0110 = 2 C4 0111 = 2 C3 1000 = 2 C2 1001 = 2 C1 1010 = 2 0 1011 = 2 1 9 output round enable 0 = enabled 1 = disabled t able 2. c ontrol r egister 1 C a ddress 001h grammed to decimate by 2 to 16 (see decimation section and table 1). shften enables and disables the shifting of data through the decima- tion registers. when shften is low, data on ina 9-0 and inb 9-0 can be latched into the device and data can be shifted through the decimation registers. when shften is high, data on ina 9-0 and inb 9-0 can not be latched into the device and data in the input and decimation registers is held. data feedback circuitry is positioned between the forward and reverse decimation registers. it controls how data from the forward decimation path is fed to the reverse decimation path. the feedback circuitry can either reverse the data order or pass the data unchanged to the reverse decimation path. the mux/demux sends incoming data to one of the lifos or the data feedback decimation register. the lifos and decimation register feed into a mux. this mux determines if one of the lifos or the decimation register sends data to the reverse decimation path. if the data order needs to be reversed before being sent to the reverse decimation path (for example, when decimating), data reversal mode should be enabled by setting bit 4 of control register 1 to 0. when data reversal is enabled, data from the forward decimation path is written into one of the lifos in the data feedback section while the other lifo sends data to the reverse decimation path. when txfr goes low, the lifo sending data to the reverse decimation path becomes the lifo receiving data from the forward decimation path, and the lifo receiving data from the forward decimation path becomes the lifo sending data to the reverse decimation path. the device must see a high to low transition of txfr in order to switch lifos. the size of data blocks sent to the reverse decimation path is determined by how often txfr goes low. to send data blocks of size 8 to
devices incorporated lf43168 dual 8-tap fir filter 6 video imaging products 03/28/2000Clds.43168-h the reverse decimation path, txfr would have to be set low once every 8 clk cycles. once a data block size has been established (by asserting txfr at the proper frequency), changing the frequency or phase of txfr assertion will cause unknown results. if data should be passed to the reverse decimation path with the order unchanged, data reversal mode should be disabled by setting bit 4 of control register 1 to 1 and txfr must be set low. when data rever- sal is disabled, data from the forward decimation path is written into the data feedback decimation register. the output of this register sends data to the reverse decimation path. the delay length of this register is the same as the forward and reverse decimation register's delay length. when the lf43168 is configured to operate as a single fir filter, the forward and reverse decimation paths in filters a and b are cascaded together. the data feedback section in filter b routes data from the forward decima- tion path to the reverse decimation path. the configuration of filter b's feedback section determines how data is sent to the reverse decimation path. data going through the feedback section in filter a is sent through the decimation register. the point at which data from the forward decimation path is sent to the data feedback section is determined by whether the filter is set to have an even or odd number of filter taps. if the filter is set to have an even number of taps, the output of the third for- ward decimation register is sent to the feedback section. if the filter is set to have an odd number of taps, the data that will be output from the third forward decimation register on the next clk cycle is sent to the feedback section. accumulators the multiplier outputs are fed into an accumulator. each filter has its own accumulator. the accumulator can be set to accumulate the multiplier outputs or sum the multiplier outputs and send the result to the accumulator output register. when accen is high, both accumulators are enabled for accumulation and writing to the accumulator output registers is disabled (the registers hold their values). when accen goes low, accumulation is halted (by sending zeros to the accumulator feedback inputs) and writing to the accumula- tor output registers is enabled. mux/adder when the lf43168 is configured as two fir filters, the mux/adder is used to determine which filter drives the output port. when the lf43168 is configured as a single fir filter, the mux/adder is used to sum the outputs of the two filters and send the result to the output port. if 10-bit data and 20-bit coefficients or 20-bit data and 10-bit coefficients are required, the mux/adder can facilitate this by scaling filter bs output by 2 C10 before being added to filter as output. mux 1-0 determines what function the mux/adder performs (see table 3). the mux/adder is also used to round the output data before it is sent to the output port. output data is rounded by adding a 1 to the bit position selected using bits 5-8 of control register 1 (see table 2). for example, to round the decimation decimation by n is accomplished by only reading the lf43168s output once every n clock cycles. for example, to decimate by 10, the output should only be read once every 10 clock cycles. when not decimating, the maximum number of taps possible with a single filter in dual filter mode is eight. when decimating by n, there are n C 1 clock cycles between output readings when the filter output is not read. these extra clock cycles can be used to calculate more filter taps. as the decimation factor increases, the number of available filter taps increases also. when programmed to decimate by n, the number of filter taps for a single filter in dual filter mode increases to 8n. arithmetic logic units the alus can perform the following operations: b + a, b C a, pass a, pass b, and negate a (Ca). if fwrd is low, the forward decimation path provides the a inputs to the alus. if fwrd is high, the a inputs are set to "0". if rvrs is low, the reverse decimation path provides the b inputs to the alus. if rvrs is high, the b inputs are set to "0". fwrd, rvrs, and the filter configuration determine which alu operation is performed. if fwrd and rvrs are both set low, and the filter is set for even-symmetric coefficients, the alu will perform the b + a operation. if fwrd and rvrs are both set low, and the filter is set for odd-symmetric coefficients, the alu will perform the b C a operation. if fwrd is set low, rvrs is set high, and the filter is set for even- symmetric coefficients, the alu will perform the pass a operation. if fwrd is set low, rvrs is set high, and the filter is set for odd-symmetric coefficients, the alu will perform the negate a operation. if fwrd is set high, rvrs is set low, and the filter is set for either even or odd-symmetric coefficients, the alu will perform the pass b operation. mux 1-0 function 00 filter a + filter b (filter b scaled by 2 C10 ) 01 filter a + filter b 10 filter a 11 filter b t able 3. mux 1-0 f unction
devices incorporated video imaging products 7 lf43168 dual 8-tap fir filter 03/28/2000Clds.43168-h output to 16 bits, bits 5-8 of control register 1 should be set to 0011. this will cause a 1 to be added to bit position 2 C7 . symmetric coefficients the lf43168 filter architecture is optimized for symmetric filter coeffi- cient sets. figure 3 shows examples of the different types of symmetric coefficient sets. in even-symmetric sets, each coefficient value appears twice (except in odd-tap sets where the middle value appears only once). in odd-symmetric sets, each coefficient appears twice, but one value is positive and one is negative. if the two data input values that will be multiplied by the same coefficient are added or subtracted before being sent to the filter multiplier, the number of multipliers needed for an n-tap filter is cut in half. therefore, an 8-tap filter can be implemented with four multi- pliers if a symmetric coefficient set is used. filter configurations figures 4-6 show the data paths from filter input to filter multipliers for all symmetric coefficient filters. figure 7 shows the interleaved coefficient filter configuration. each diagram shows one of the two fir filters when the device is configured for dual filter mode. the diagrams can be expanded to include both filters when the device is configured for single filter mode. even-symmetric coefficient filters figure 4 shows the two possible configurations when the device is programmed for even-symmetric coefficients and no decimation. note that coefficient 3 on the odd- tap filter must be divided by two to get the correct result (the coefficient must be input to the device already divided by two). f igure 3. s ymmetric c oefficient s et e xamples 1 2 3 4 5 6 7 8 even-tap, even-symmetric coefficient set odd-tap, even-symmetric coefficient set 1 2 3 4 5 6 7 8 even-tap, odd-symmetric coefficient set 1 2 3 4 5 6 7 f igure 4. e ven -s ymmetric c oefficient f ilter c onfigurations (n o d ecimation ) coef 0 coef 1 coef 2 coef 3 b + a ab b + a ab b + a ab b + a ab data in even-tap filter coef 0 coef 1 coef 2 coef 3 b + a ab b + a ab b + a ab b + a ab data in 2 odd-tap filter
devices incorporated lf43168 dual 8-tap fir filter 8 video imaging products 03/28/2000Clds.43168-h figure 5 shows the two possible configurations when the device is programmed as a decimating, even- symmetric coefficient filter. the delay length of the decimation registers will be equal to the decimation factor that the device is programmed for. since only four coefficients (effectively eight) can be sent to the filter multipli- ers on a clock cycle, it may be neces- sary (depending on the coefficient set) to change the coefficients fed to the multipliers on different clk cycles for filters with more than eight taps. note that for the odd-tap filter, the middle coefficient of the coefficient set must be divided by two to get the correct result. odd-symmetric coefficient filters figure 6 shows the two possible configurations when the device is programmed for odd-symmetric coefficients. note that odd-tap, odd- symmetric coefficient filters are not possible. f igure 5. d ecimating , e ven -s ymmetric c oefficient f ilter c onfigurations coef 0 coef 1 coef 2 coef 3 b + a ab b + a ab b + a ab b + a ab data in mux lifo a lifo b demux nnn nnn n = delay length (decimation factor) even-tap filter coef 0 coef 1 coef 2 coef 3 b + a ab b + a ab b + a ab b + a ab data in mux lifo a lifo b demux nnn nnn n = delay length (decimation factor) delay stage n C 1 output odd-tap filter f igure 6. o dd -s ymmetric c oefficient f ilter c onfigurations coef 0 coef 1 coef 2 coef 3 b C a ab b C a ab b C a ab b C a ab data in even-tap filter ( no decimation ) coef 0 coef 1 coef 2 coef 3 b C a ab b C a ab b C a ab b C a ab data in mux lifo a lifo b demux nnn nnn n = delay length (decimation factor) decimating, even-tap filter
devices incorporated video imaging products 9 lf43168 dual 8-tap fir filter 03/28/2000Clds.43168-h interleaved coefficient filters figure 7 shows the filter configuration when the device is programmed for interleaved coefficients. an inter- leaved coefficient set contains two separate odd-tap, even-symmetric coefficient sets which have been interleaved together (see figure 8). if two data sets are interleaved into the same serial data stream, they can both be filtered by different coefficient sets if the two coefficient sets are also interleaved. the lf43168 is config- ured as an interleaved coefficient filter by programming the device for interleaved coefficient sets, even- symmetric coefficients, odd number of filter taps, and data reversal disabled. note that coefficient 3, in figure 7, must be divided by two to get the correct result. asymmetric coefficient filters it is possible to have asymmetric coefficient filters. asymmetric coeffi- cient sets do not exhibit even or odd symmetric properties. a 4-tap asym- metric filter is possible by putting the device in even-tap, pass a mode and then feeding the asymmetric coeffi- cient set to the multipliers. an 8-tap asymmetric filter is possible if the device is clocked twice as fast as the input data rate. it will take two clk cycles to calculate the output. on the first clk cycle, the reverse decimation path is selected to feed data to the filter multipliers. on the second clk cycle, the coefficients sent to the multipliers are changed (if necessary) and the forward decimation path is selected to feed data to the filter multipliers. f igure 8. i nterleaved c oefficient s et e xample interleaved coefficient set consisting of sets a and b 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 odd-tap, even-symmetric coefficient set b 1 2 3 4 5 odd-tap, even-symmetric coefficient set a 6 7 6 7 11 12 13 14 f igure 7. i nterleaved c oefficient f ilter c onfiguration coef 0 coef 1 coef 2 b + a ab b + a ab b + a ab b + a ab data in odd-tap interleaved filter nnn nnn n = delay length (decimation factor) n coef 3 2
devices incorporated lf43168 dual 8-tap fir filter 10 video imaging products 03/28/2000Clds.43168-h storage temperature ........................................................................................................... C65c to +150c operating ambient temperature ........................................................................................... C55c to +125c v cc supply voltage with respect to ground ............................................................................ C0.5 v to +7. 0v input signal with respect to ground ............................................................................... C0.5 v to v cc + 0.5 v signal applied to high impedance output ...................................................................... C0.5 v to v cc + 0.5 v output current into low outputs ................................................................................................ ............. 25 ma latchup current ................................................................................................................ ............... > 400 ma m aximum r atings above which useful life may be impaired (notes 1, 2, 3, 8) o perating c onditions to meet specified electrical and switching characteristics mode temperature range (ambient) supply voltage active operation, commercial 0c to +70c 4.75 v v cc 5.25 v active operation, military C55c to +125c 4.50 v v cc 5.50 v symbol parameter test condition min typ max unit v oh output high voltage v cc = min., i oh = C2.0 ma 2.6 v v ol output low voltage v cc = min., i ol = 4.0 ma 0.4 v v ih input high voltage 2.0 v cc v v il input low voltage (note 3) 0.0 0.8 v i ix input current ground v in v cc (note 12) 10 a i oz output leakage current ground v out v cc (note 12) 10 a i cc1 v cc current, dynamic (notes 5, 6) 300 ma i cc2 v cc current, quiescent (note 7) 500 a c in input capacitance t a = 25c, f = 1 mhz 12 pf c out output capacitance t a = 25c, f = 1 mhz 12 pf e lectrical c haracteristics over operating conditions (note 4)
devices incorporated video imaging products 11 lf43168 dual 8-tap fir filter 03/28/2000Clds.43168-h lf43168C 30 22 15 symbol parameter min max min max min max t cyc cycle time 30 22 15 t pw clock pulse width 12 8 7 t s input setup time 15 12 5 t h input hold time 0 0 0 t wp write period 30 22 15 t wpw write pulse width 12 10 7 t whch write high to clock high 5 3 2 t cws cin 9-0 setup time 12 10 5 t cwh cin 9-0 hold time 0 0 0 t aws address setup time 10 8 5 t awh address hold time 0 0 0 t d output delay 14 12 11 t ena three-state output enable delay (note 11) 12 12 12 t dis three-state output disable delay (note 11) 12 12 12 c ommercial o perating r ange notes 9, 10 (ns) switching characteristics s witching w aveforms clk inputs/ cin 9-0 t pw t pw t cyc a 8-0 oel out 27-0 t h t s t d t dis high impedance t ena oeh wr t aws t awh t cwh t cws t whch *includes ina 9-0 , inb 9-0 , csel 4-0 , accen, mux 1-0 , shften, fwrd, rvrs, and txfr. controls* t wpw t wpw t wp
devices incorporated lf43168 dual 8-tap fir filter 12 video imaging products 03/28/2000Clds.43168-h 1234567890123456789012345678901212345678901234 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1234567890123456789012345678901212345678901234 lf43168C 39 * 30 * 22 * symbol parameter min max min max min max t cyc cycle time 39 30 22 t pw clock pulse width 15 12 8 t s input setup time 17 15 12 t h input hold time 0 0 0 t wp write period 39 30 22 t wpw write pulse width 15 12 10 t whch write high to clock high 8 5 3 t cws cin 9-0 setup time 15 12 10 t cwh cin 9-0 hold time 0 0 0 t aws address setup time 10 10 8 t awh address hold time 0 0 0 t d output delay 17 15 12 t ena three-state output enable delay (note 11) 12 12 12 t dis three-state output disable delay (note 11) 12 12 12 m ilitary o perating r ange notes 9, 10 (ns) switching characteristics s witching w aveforms clk inputs/ cin 9-0 t pw t pw t cyc a 8-0 oel out 27-0 t h t s t d t dis high impedance t ena oeh wr t aws t awh t cwh t cws t whch *includes ina 9-0 , inb 9-0 , csel 4-0 , accen, mux 1-0 , shften, fwrd, rvrs, and txfr. controls* t wpw t wpw t wp *d iscontinued s peed g rade
devices incorporated video imaging products 13 lf43168 dual 8-tap fir filter 03/28/2000Clds.43168-h 1. maximum ratings indicate stress specifications only. functional oper- ation of these products at values beyond those indicated in the operating condi- tions table is not implied. exposure to maximum rating conditions for ex- tended periods may affect reliability. 2. the products described by this spec- ification include internal circuitry de- signed to protect the chip from damag- ing substrate injection currents and ac- cumulations of static charge. neverthe- less, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive electrical stress values. 3. this device provides hard clamping of transient undershoot and overshoot. in- put levels below ground or above v cc will be clamped beginning at C0.6 v and v cc + 0.6 v. the device can withstand indefinite operation with inputs in the range of C0.5 v to +7.0 v. device opera- tion will not be adversely affected, how- ever, input current levels will be well in excess of 100 ma. 4. actual test conditions may vary from those designated but operation is guar- anteed as specified. 5. supply current for a given applica- tion can be accurately approximated by: where n = total number of device outputs c = capacitive load per output v = supply voltage f = clock frequency 6. tested with all outputs changing ev- ery cycle and no load, at a 20 mhz clock rate. 7. tested with all inputs within 0.1 v of v cc or ground, no load. 8. these parameters are guaranteed but not 100% tested. ncv f 4 2 notes 9. ac specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 v (except t dis test), and input levels of nominally 0 to 3.0 v. output loading may be a resistive divider which provides for specified i oh and i ol at an output voltage of v oh min and v ol max respectively. alternatively, a diode bridge with upper and lower current sources of i oh and i ol respectively, and a balancing voltage of 1.5 v may be used. parasitic capacitance is 30 pf minimum, and may be distributed. this device has high-speed outputs ca- pable of large instantaneous current pulses and fast turn-on/turn-off times. as a result, care must be exercised in the testing of this device. the following measures are recommended: a. a 0.1 f ceramic capacitor should be installed between v cc and ground leads as close to the device under test (dut) as possible. similar capacitors should be installed between device v cc and the tester common, and device ground and tester common. b. ground and v cc supply planes must be brought directly to the dut socket or contactor fingers. c. input voltages should be adjusted to compensate for inductive ground and v cc noise to maintain required dut input levels relative to the dut ground pin. 10. each parameter is shown as a min- imum or maximum value. input re- quirements are specified from the point of view of the external system driving the chip. setup time, for example, is specified as a minimum since the exter- nal system must supply at least that much time to meet the worst-case re- quirements of all parts. responses from the internal circuitry are specified from the point of view of the device. output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 11. for the t ena test, the transition is measured to the 1.5 v crossing point with datasheet loads. for the t dis test, the transition is measured to the 200mv level from the measured steady-state output volt age with 10ma loads. the balancing volt- age, v th , is set at 3.5 v for z-to-0 and 0-to-z tests, and set at 0 v for z- to-1 and 1-to-z tests. 12. these parameters are only tested at the high temperature extreme, which is the worst case for leakage current. s1 i oh i ol v th c l dut oe 0.2 v t dis t ena 0.2 v 1.5 v 1.5 v 3.5v vth 1 z 0 z z 1 z 0 1.5 v 1.5 v 0v vth v ol * v oh * v ol * v oh * measured v ol with i oh = C10ma and i ol = 10ma measured v oh with i oh = C10ma and i ol = 10ma f igure b. t hreshold l evels f igure a. o utput l oading c ircuit
devices incorporated lf43168 dual 8-tap fir filter 14 video imaging products 03/28/2000Clds.43168-h plastic j-lead chip carrier (j3) lf43168jc30 lf43168jc22 LF43168JC15 84-pin speed 30 ns 22 ns 15 ns ordering information 1 2 3 4 5 6 7 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 84 83 82 81 80 79 44 43 45 46 47 49 38 37 39 40 41 42 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 top view 8 9 10 11 78 77 76 75 36 35 34 33 50 51 52 53 cin 7 cin 6 cin 5 cin 4 gnd cin 3 cin 2 cin 1 cin 0 ina 9 ina 8 ina 7 ina 6 ina 5 v cc ina 4 ina 3 ina 2 ina 1 ina 0 inb 9 rvrs fwrd shften txfr accen v cc clk gnd oeh out 27 out 26 out 25 out 24 out 23 out 22 out 21 out 20 out 19 out 18 out 17 v cc inb 8 inb 7 inb 6 inb 5 gnd inb 4 inb 3 inb 2 inb 1 inb 0 oel out 9 out 10 v cc out 11 out 12 out 13 out 14 out 15 out 16 gnd cin 8 cin 9 csel 4 csel 3 csel 2 csel 1 csel 0 v cc a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 gnd wr mux 1 mux 0 C40c to +85c c ommercial s creening 0c to +70c c ommercial s creening
devices incorporated video imaging products 15 lf43168 dual 8-tap fir filter 03/28/2000Clds.43168-h plastic quad flatpack (q2) lf43168qc30 lf43168qc22 lf43168qc15 100-pin speed 30 ns 22 ns 15 ns ordering information cin 8 nc cin 7 nc cin 6 cin 5 cin 4 gnd gnd cin 3 cin 2 cin 1 cin 0 ina 9 ina 8 ina 7 ina 6 ina 5 v cc v cc ina 4 ina 3 ina 2 ina 1 ina 0 nc nc inb 9 inb 8 inb 7 cin 9 csel 4 csel 3 csel 2 csel 1 csel 0 v cc v cc a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 gnd gnd wr mux 1 mux 0 rvrs nc fwrd shften txfr accen v cc v cc clk gnd gnd oeh out 27 out 26 out 25 out 24 out 23 out 22 out 21 out 20 out 19 out 18 out 17 nc v cc v cc gnd gnd inb 6 inb 5 gnd gnd inb 4 inb 3 inb 2 inb 1 inb 0 oel out 9 out 10 v cc v cc out 11 out 12 out 13 out 14 out 15 out 16 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 C40c to +85c c ommercial s creening 0c to +70c c ommercial s creening
devices incorporated lf43168 dual 8-tap fir filter 16 video imaging products 03/28/2000Clds.43168-h 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 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ceramic pin grid array (g6) 84-pin speed ordering information 0c to +70c c ommercial s creening C55c to +125c mil-std-883 c ompliant C55c to +125c c ommercial s creening a b c d e f g h j k l top view through package (i.e., component side pinout) 12345 6 7 8 9 10 11 csel 4 cin 7 cin 6 gnd cin 1 ina 9 ina 5 ina 3 ina 0 inb 8 inb 6 csel 3 cin 9 cin 2 ina 8 ina 7 inb 7 inb 5 csel 1 csel 2 gnd inb 4 a 8 v cc csel 0 inb 3 inb 2 inb 1 a 7 a 2 a 6 oel inb 0 out 11 a 4 a 3 a 5 out 9 v cc out 10 a 1 a 0 out 13 out 12 cin 8 cin 5 cin 4 cin 3 cin 0 v cc ina 6 ina 4 ina 2 ina 1 inb 9 gnd mux 1 clk out 26 out 25 out 16 out 14 wr mux 0 fwrd accen gnd out 22 out 23 out 20 out 17 v cc out 15 rvrs shften txfr v cc oeh out 27 out 24 out 21 out 19 out 18 gnd discontinued package

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